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VLSI memory chip design

1. An Introduction to Memory Chip Design

Several essential inventions and innovations, and subsequent sustained efforts [1.1] toward high densities have paved the way to large-scale integrated circuit (LSI) memories, as shown in Fig. 1.1 [1.2]. Since two epoch-making announcements accompanying the start of LSI memory production in 1970 [the first extensive usage of a semiconductor memory chip for the IBM 370 mainframe computers, and the first sales of a 1-Kb dynamic random access memory (DRAM), named the 1103, from Intel], the increase in memory chip capacity has skyrocketed with the help of the ever-higher-density MOS / CMOS design and technology. The resultant LSI memories have given computers, networks, and almost everything with electrical components the benefit of a dramatically reduced cost per bit and far superior performance. Data processors and data terminals, such as personal computers, workstations, and POS terminals, as well as telephone exchanges, digital televisions, and numerical control machines, could not have been produced without them.

2. The Basics of RAM Design and Technology

Advances in memory chip technology have been supported by extensive technologies, such as high-density, high-speed device and circuit technology, lithography and fabrication process technology, and high-density packaging technology. In this chapter, the basics of some of the above supporting technologies are discussed.

3. DRAM Circuits

The intensive research and development (R&D) directed toward DRAMs has rapidly increased memory-chip capacity by more than six orders (1 Kb to 4 Gb) at the R&D level over the past 30 years [3.1] since the advent of DRAMs in the early 1970s. As a result, 64-256 Mb DRAMs are now at the volume production level. Such rapid progress in DRAM density has led to their playing an important role in enhancing the performance and reducing the cost of electronic systems such as large computers, workstations, personal computers (PCs), and so on. The quadrupling of memory capacity, as shown in Fig. 3.1, through high-density technology has contributed to this progress. High-performance circuits aimed at higher speed and lower dissipation, which have been achieved in past despite the ever-increasing chip area with increased memory capacity (Fig. 3.1), have also benefited system designers.

4. High signal-to-noise ratio DRAM design and technology

One of the main contributions to DRAM advances is the one-transistor, one-capacitor (1-T) cell, as explained in Chaps. 1 and 3. The cell has been universally used for over 25 years, because it has the highest density. The drawbacks - no gain and the existence of leakage currents in the cell - have been overcome by successive developments in high signal-to-noise (S / N) ratio designs and technologies. Moreover, the multidivision of data lines by using multilevel metal wiring, explained in Chap. 3 has not only allowed a high-speed and low-power array, but also a high S / N array, while limiting the increase in chip area. Without high S / N designs and technologies, the kilobit and megabit eras would not have been developed at all. In the multigigabit era, however, there are many challenges to realizing high S / N cell design to cope with the ever-decreasing cell area and ultra-low-voltage operations. The development of higher-permittivity materials for capacitor dielectric films, while keeping the fabrication process as simple as possible, and the suppression of the random design-parameter variations of MOSFETs, which are prominent below 0.1 μm, are good examples. However, it will be more difficult than ever to accomplish these things, because of fabrication and physical limits.

5. On-Chip Voltage Generators

On-chip voltage generation [5.1-5.8] is becoming increasingly important for memory LSI design, as well as for other LSI designs. This importance is being accelerated by a recent trend toward lower-voltage operation. In the past, generators have been widely used in commercial memory chips such as DRAMs and Flash memories, as explained in Chap. 1. For example, DRAM chips have needed various kinds of power-supply voltages, which have been generated internally by using a single external supply-voltage (V.DD), as shown in Fig. 5.1. A negative voltage (VBB) is a substrate bias voltage supplied to an NMOS memory-cell array to ensure stable memory-cell operation. A boosted dc voltage (VDH or VPP) is for word bootstrapping, to eliminate the drop in the cell VT. A half-VDD (or VDL) achieves a half-VDD (or VDL) data-line precharge for power reduction, and a half-VDD (or VDL) cell-capacitor plate for high S / N ratio design, as explained in Chaps. 3 and 4. Modern commercial DRAMs of 16 Mb and beyond even incorporate an on-chip voltage down-converter, which lowers V.DD to VDL, by using an internal reference voltage (VREF), to simultaneously achieve high reliability of small devices and power-supply standardization. Flash memories have also used an extremely boosted word-line voltage, and even a negative voltage, to relaxing a stress voltage to a memory-cell FET, as explained in Chap. 1. Schematic circuits for generating these internal voltages are shown in Fig. 5.2.

6. High-performance subsystem memories

In the past, the high-speed SRAM cache and the DRAM main memory have contributed to enhancing the performance of hierarchical memory systems (Fig. 6.1) in personal computers (PCs), workstations, servers, and so on. Recently, however, to bridge the ever-increasing speed gap between microprocessor units (MPUs) and main memories, high-speed DRAMs [6.1–6.5] such as the synchronous DRAM (SDRAM) and the Rambus DRAM have become increasingly important. These DRAMs incorporate memory subsystem technologies that memory system designers have used to enhance not only access and cycle times, but also throughput. Here, throughput is defined as the product of bus width and frequency. The resulting high throughput of the DRAM chips has been indispensable even for PC graphics, image processing, and other multimedia applications [6.6–6.8]. In particular, high throughput is a key to high-performance graphics systems, as shown in Fig. 6.1. There are two missions for a graphics memory. One is to output data to display devices such as the cathode-ray tube (CRT). The other is to transfer drawing data to and from the video processor. Display performance has achieved 200 Mbyte / s, but the perception of the human eye is limited in terms of resolution and after-image, and therefore the high-performance requirement is getting saturated. The need for high-drawing performance, however, is increasing incessantly.

7. Low-Power Memory Circuits

The low-power RAM circuit [7.1-7.4] is a major area of ​​interest in low-power LSI research. Successive advances in the low-power RAM circuit have been able to suppress chip-power consumption, which increases with increasing memory capacity, chip area, and speed. As a result, these advances - coupled with high-density memory-cell technology - have allowed chip power consumption to be maintained or lowered (Fig. 7.1), although the memory capacity of DRAM chips has increased rapidly by over six orders (1 Kb to 4 Gb) over the past 30 years. Consequently, the low-power RAM circuit has realized low-cost, high-reliability chips because it allows plastic packaging, a low operating current, and a low junction temperature. In addition, it has managed the ever-increasing memory subsystem power caused by the increasingly high throughput requirements of various processing systems such as personal computers. Moreover, it forms not only the basis of other LSI memory chips, such as Flash memory and ROM, but also the basis of on-chip memory subsystems, such as embedded DRAMs (merged DRAM and logic) [7.3] and SRAM caches, both of which have become increasingly important in modern memory systems.

8. Ultra-Low-Voltage Memory Circuits

The reduction of the operating voltage is essential not only to reduce power dissipation, but also to ensure reliability for miniaturized devices. Further reduction of the supply voltage allows users to design ultra-low-power systems or battery-based mobile equipment. One target is 0.9 V, the minimum voltage of a NiCd cell. Even in this case, higher performance will eventually be required, due to the ever-increasing demand for digital signal processing capability. To simultaneously achieve low voltage and high-speed operation, both device miniaturization and threshold voltage (VT) scaling are indispensable. Fortunately, the state-of-the-art device technology in miniaturization has at last progressed to the extent of realizing quite high speed even at low voltages of less than 2 V. Even SOI CMOS technology - more suitable for ultra-low-voltage operations - is being intensively developed. V.T scaling, however, is highlighted as an emerging issue, because the reduction of VT increases the MOSFET subthreshold current [8.1-8.6], even in CMOS chips. The resulting dc current eventually dominates even the active chip current, losing the low-power advantage of CMOS circuits that we take for granted today. today. The issue is essential not only for the design of large-capacity RAM chips with a feature size of 0.1 µm or less in the future, but also for the design of ultralow-voltage LSIs such as medium memory-capacity RAM chips and MPU chips with an existing fabrication process tailored to scaled V.T.